
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT? Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Synchronous Truth Table (1)
CEN
L
L
L
R/ W
L
H
X
CE 1 ,
CE 2 (5)
L
L
X
ADV/ LD
L
L
H
BW x
Valid
X
Valid
ADDRESS
USED
External
External
Internal
PREVIOUS CYCLE
X
X
LOAD WRITE /
CURRENT CYCLE
LOAD WRITE
LOAD READ
BURST WRITE
I/O
(One cycle later)
D (7)
Q (7)
D (7)
BURST WRITE
(Advance burst counter) (2)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
Q (7)
BURST READ
(Advance burst counter) (2)
SUSPEND
L
L
H
X
X
X
H
X
X
L
H
X
X
X
X
X
X
X
X
DESELECT / NOOP
X
DESELECT or STOP (3)
NOOP
(4)
HIZ
HIZ
Previous Value
5282 tbl 08
NOTES:
1. L = V IL , H = V IH , X = Don’t Care.
2. When ADV/ LD signal is sampled high, the internal burst counter is incremented. The R/ W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/ W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either ( CE 1 , or CE 2 is sampled high or CE 2 is sampled low) and ADV/ LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE 1 = L, CE 2 = L and CE 2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes
(1)
WRITE BYTE 2 (I/O[8:15], I/O P2 )
WRITE BYTE 3 (I/O[16:23], I/O P3 )
OPERATION
READ
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/O P1 ) (2)
(2)
(2,3)
WRITE BYTE 4 (I/O[24:31], I/O P4 ) (2,3)
NO WRITE
R/ W
H
L
L
L
L
L
L
BW 1
X
L
L
H
H
H
H
BW 2
X
L
H
L
H
H
H
BW 3 (3)
X
L
H
H
L
H
H
BW 4 (3)
X
L
H
H
H
L
H
5282 tbl 09
NOTES:
1. L = V IL , H = V IH , X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
Interleaved Burst Sequence Table ( LBO =V DD )
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
Second Address
Third Address
Fourth Address (1)
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
9
6.42
5282 tbl 10